HCLTech
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Engineering & R&D

Technical Architect - SoC, Verilog, UVM, C, C++

Santa Clara, United States

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Job Summary

We are seeking highly motivated Design Verification Engineers to verify a next-generation UALink Controller IP used in AI and HPC platforms. The engineer will develop scalable verification environments capable of achieving functional, protocol, and performance closure for one of the industry's highest-bandwidth interconnect controllers.

The role requires expertise in constrained-random verification, protocol checking, coverage-driven verification, and debugging complex hardware interactions.

Key Responsibilities

  • Develop UVM-based verification environments.
  • Develop protocol-aware scoreboards.
  • Build functional coverage models.
  • Write assertions (SVA).
  • Develop protocol monitors and checkers.
  • Create directed, random, and stress tests.
  • Perform regression analysis.
  • Debug RTL issues using waveform analysis and transaction logs.
  • Collaborate closely with RTL designers.
  • Drive verification closure using metrics.

Skill Requirements

  • Strong communication and cross-functional collaboration with architecture, design teams.
  • Excellent debugging and problem-solving skills.
  • SystemVerilog
  • UVM
  • SVA
  • Python, Perl or Tcl

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Other Requirements

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