HCLTech
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Engineering & R&D

Technical Architect

King, United States

Verified applicants only — secured by Polyguard

Job Summary

The Technical Program Manager (TPM) – Advanced SoC Physical Design is responsible for leading end-to-end execution of complex SoC implementation programs from RTL handoff through GDSII signoff. The role combines deep technical expertise in advanced-node Physical Design with strong program leadership, customer engagement, risk management, and cross-functional coordination across Design, Verification, DFT, Package, CAD, and Silicon Validation teams.

The TPM serves as the single point of accountability for delivery predictability, schedule adherence, quality, customer communication, and successful tape-out execution. The ideal candidate possesses strong full-chip implementation experience across advanced process technologies and has demonstrated success driving large-scale ASIC/SoC programs to production.

Key Responsibilities

  1. Program & Delivery Ownership
    1. Own end-to-end delivery of full-chip SoC Physical Design and implementation programs.
    2. Define execution plans, milestones, resource strategy, dependencies, and tape-out schedules.
    3. Drive predictable delivery across RTL-to-GDSII implementation activities.
    4. Manage program risks, dependencies, escalations, and mitigation plans.
    5. Ensure adherence to schedule, quality, cost, and customer commitments.
    6. Lead program reviews, status reporting, MBR/QBR discussions, and executive communication.
  1. Technical Leadership

Provide technical oversight across:

    1. Design Planning & Floorplanning
    2. Power Planning / PDN
    3. Synthesis
    4. Place & Route
    5. Clock Tree Synthesis (CTS)
    6. Timing Closure
    7. Signal Integrity
    8. Power Optimization
    9. Physical Verification
    10. EM/IR Analysis
    11. Signoff & Tape-out
    12. Drive PPA (Performance, Power, Area) optimization strategies.
    13. Guide teams on advanced-node implementation challenges and methodologies.
    14. Review implementation quality, technical risks, and closure readiness
  1. Full-Chip Integration & Cross-Functional Collaboration
    1. Coordinate execution across RTL Design, Verification, Physical Design, DFT, Package, CAD, Library, IP, and Foundry teams.
    2. Drive alignment on design handoffs, integration milestones, and signoff criteria.
    3. Resolve technical and schedule conflicts impacting tape-out readiness.
    4. Ensure smooth execution of RTL-to-GDSII flow across multiple stakeholders
  1. Customer Engagement
    1. Act as primary customer-facing technical and program interface.
    2. Drive scope clarification, estimation reviews, milestone alignment, and delivery commitments.
    3. Lead customer reviews and executive updates.
    4. Proactively manage customer expectations and escalations
  1. Team Leadership & Capability Development
    1. Build and lead high-performing implementation teams.
    2. Mentor technical leads and program engineers.
    3. Assess team capabilities, identify skill gaps, and develop succession plans.
    4. Support staffing, onboarding, resource forecasting, and utilization planning
  1. Governance & Operational Excellence
    1. Establish execution dashboards, metrics, and KPIs.
    2. Drive continuous improvement, automation, and methodology enhancements.
    3. Champion AI/ML and EDA productivity solutions where applicable.
    4. Ensure compliance with organizational and customer processes

Skill Requirements

  1. Physical Design Expertise
  • Strong full-chip SoC implementation experience from RTL-to-GDSII.
  • Expertise in:
  • Floorplanning
  • Power Planning
  • Synthesis
  • P&R
  • CTS
  • Timing Closure
  • Physical Verification
  • EM/IR Signoff
  • ECO Management
  • Deep understanding of advanced-node design challenges (5nm/3nm and below preferred).
  1. EDA Tools
  • Strong exposure to Synopsys and/or Cadence implementation flows.
  • Familiarity with:
  • ICC2
  • Fusion Compiler
  • Innovus
  • Tempus
  • PrimeTime
  • RedHawk
  • Calibre
  • Voltus
  • StarRC
  1. SoC Architecture Knowledge
  • Understanding of:
  • CPU/GPU based architectures
  • High-speed interfaces
  • Memory subsystems
  • NoC/Fabric architectures
  • Low-power design methodologies
  • Multi-voltage and power-domain implementations
  1. Program Management
  • Experience managing large global engineering teams.
  • Strong project planning, budgeting, forecasting, and risk management skills.

Expertise in stakeholder communication and executive reporting

Other Requirements

Experience & Qualifications

Required

  • B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related field.
  • 12–18+ years of semiconductor industry experience.
  • Minimum 5+ years leading SoC implementation programs or full-chip tape-outs.
  • Proven experience managing customer-facing engagements and large delivery teams.
  • Track record of successful silicon tape-outs at advanced process nodes.

Preferred

  • Experience managing multi-site/global development teams.
  • Exposure to HPC, AI/ML, Data Center, Networking, Mobile, or Automotive SoCs.
  • PMP, PgMP, Agile, or equivalent program management certification.

Experience with AI-assisted design methodologies and EDA automation

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